Solving a Pesky PLL tuning issue for an RF transceiver

As a debut article, I’d like to share about one of the problems solved on a PLL circuit and problems when the product transferred to production calibration. Without revealing too many details due to sensitivities of trade secrets and all, I still would like to share how I  worked through this  problem on  a medical telemetry transceiver.

Let me first set the stage.  Let’s say a product is to be deployed worldwide but each geographical region has different frequency channel  allocations for the ISM band you are trying to meet.  In an effort to save design costs, a single PCB was fabricated in trying to meet all the 8 different operating bands. Each option had a modified BOM to and a programmable PLL  and DAC that allowed for tuning each of the options.

4th order Loop Filter basic representation.

On the production floor we had a coarse tune adjustment and fine tune adjustment used the same PLL  and VCO.  Finding the sweet spot for all frequency ranges ( 400- 900MHz) AND gain variations for course versus fine meant having a challenging design constrained  to changing a few passive components for a 4^th order loop filter for the PLL.

The main purpose of the loop filter is to act as a low pass filter (LPF) for the DC adjustments to the VCO.  It needs to be responsive enough for the charge pump changes in the PLL, yet not too wide of a bandwidth  or it allows the VCO to track harmonics of the frequency.  Ideally, you are looking for a narrow bandwidth from DC to 1K Hz in this particular setup.

There was a corner case on one of the frequency options where we had fallout in terms of yield. The problem showed up on the production floor during course tuning  when the board would go into an unwanted 800Hz oscillation.  Prior attempts to duplicate this particular problem  on the bench failed. Accepting the challenge I rolled up my sleeves made the following steps:

STEP 1: Design a test jig that can control just the radio module and allows access to the R and N counter values of the PLL as well as make the DAC adjustments for the course tuning. The schematic below is a representative interface I worked with

Test jig to recreate problem in the lab.

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I had a simple SW interface to change the register for N and R values of the divide-by-N PLL  values on the fly.

STEP 2: Duplicate the same process as on the production floor. Once I was able to control the PLL and tune the VCO, I wanted to make sure the same sequences on the production floor were followed.  With this setup in the lab,  I was able to duplicate the tuning sequence on the production floor on the radio module under test and recreate the problem. It was important to follow the same algorithm as on the floor which meant starting from a MAX setting on the course tuning. In doing so, I found the corner case where the unwanted 700-800 Hz  oscillation was taking place.

Step 3: Understand the stability over the different gain adjustment in the closed loop.  The loop filter was designed for a fine tuning VCO gain ( k factor) of 6 MHz/V.  However, with  the course adjustment used on the floor, the frequency of the VCO changes   at a rate of 15 Mhz/V.  This created a 2.5 Delta in the anticipated gain when the loop filter values were chosen.

Step 4: Closed loop versus open Loop transfer characteristics: In the lab, I inserted a Gaussian noise in the loop to see the response of the circuit over a range of Frequencies at different VCO gain settings.  I made do with what equipment was available in the lab. I use a very old HP 3562A Dynamic Signal Analyzer.  It plotted the dynamic response of the closed loop circuit with the odd gain setting. Low and behold, was a pole at the unwanted ringing frequency seen on the production floor.

Screen capture of the unwanted Pole causing the ringing at 706Hz

 

Step 5: Finding a practical solution :  The loop filter values didn’t consider  the higher VCO gain k-factor when tuned on the production floor. Values needed to be considered  for dynamic gain adjustments. The problem is that the use case for  the course gain will not be used once production calibration is  complete. Could a middle ground be reached which allowed production to go ahead without changing the process and still not impact performance of the transceiver?

I found a mathematical model that broke down the time constants for the orders in the loop filter.

In order to look at the closed loop transfer function the open loop characteristics needed to be defined first. The impedance of the open loop filter can be expressed in terms of the time constants for each order of the filter .

But the closed loop gain needs to be considered for the stability factor. From the impedance of the open loop gain is determined as a function of the gain of the charge pump(KΦ), the VCO gain (K_VCO)  as follows;

The closed loop transfer function takes into account the N counter  of the PLL . The N counter value is the output frequency of the VCO divided by the reference comparison frequency from the VCTXO.  Generically this expression looks like:

In order to find the stability of the circuit the following Routh criteria must be met

During the High gain, R2 and R3 were picked such that the stability factor was <1 after everything was crunched.  I managed to find the a set of values that increased the stability with a moderate tradeoff in overall loop bandwidth which still met all our operational and regulatory specifications.

With a minor BOM change,  we went from a yield of less than 50% to one that was over 94% without doing a redesign or having to validate a new production calibration procedure.

Problem SOLVED!

I thought I’d share this. Hope you find it useful.

George Duval

RF Analog Engineer.